 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| VNQ5050K-E QUAD CHANNEL HIGH SIDE DRIVER FOR AUTOMOTIVE APPLICATIONS ADVANCE DATA Table 1. General Features TYPE VNQ5050K-E (*) Per channel Figure 1. Package RDS(on) 50m (*) Iout 12A VCC 41V OUTPUT CURRENT: 12A 3.0 V CMOS COMPATIBLE INPUT s STATUS DISABLE s ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s OUTPUT STUCK TO VCC DETECTION s OPEN DRAIN STATUS OUTPUT s UNDERVOLTAGE SHUT-DOWN s s OVERVOLTAGE CLAMP s THERMAL SHUT DOWN s CURRENT AND POWER LIMITATION s VERY LOW STAND-BY CURRENT s PROTECTION AGAINST LOSS OF GROUND AND LOSS OF VCC s VERY LOW ELECTROMAGNETIC SUSCEPTIBILITY s OPTIMIZED ELECTROMAGNETIC EMISSION s REVERSE BATTERY PROTECTION (**) s IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE s PowerSSO-24 DESCRIPTION The VNQ5050K-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes Package PowerSSO-24 Note: (**) See application schematic at page 9. The device detects open load condition both in on and off state, when STAT_DIS is left open or driven low. Output shorted to VCC is detected in the off state. When STAT_DIS is driven high, the STATUS pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention. . Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Tube VNQ5050K-E Tape and Reel VNQ5050KTR-E Rev. 1 October 2004 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/13 VNQ5050K-E Figure 2. Block Diagram VCC OUTPUT1 GND INPUT1 CLAMP 1 STATUS1 STAT_DIS LOGIC INPUT2 STATUS2 OPENLOAD ON 1 INPUT3 STATUS3 INPUT4 STATUS4 OPENLOAD OFF 1 VCC OUTPUT4 OVERTEMP 1 . CURRENT LIMITER 1 CONTROL & PROTECTION STATUS3 EQUIVALENT TO CHANNEL1 INPUT3 VCC OUTPUT3 DRIVER 1 CONTROL & PROTECTION STATUS2 EQUIVALENT TO CHANNEL1 INPUT2 VCC OUTPUT2 VCC CLAMP UNDERVOLTAGE PWRLIM 1 CONTROL & PROTECTION STATUS4 EQUIVALENT TO CHANNEL1 INPUT4 Table 3. Pin Function Name VCC OUTPUTn GND INPUTn STATUSn STAT_DIS Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Open drain digital diagnostic pin Active high CMOS compatible pin, to disable the STATUS pin Function Figure 3. Current and Voltage Conventions IS VCC VFn (*) VCC ISD STAT_DIS VSD IINn INPUTn VINn GND IGND STATUSn OUTPUTn IOUTn VOUTn ISTATn VSTATn (*) VFn = VCC - VOUTn during reverse battery condition 2/13 VNQ5050K-E Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins VCC GND INPUT1 STATUS1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 STAT_DIS VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4 Connection / Pin Status Floating X To Ground N.C. X X Output X Input X Through 10K resistor Table 4. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT VESD Tj Tstg DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic discharge (R=1.5k; C=100pF) Junction Operating Temperature Storage Temperature Parameter Value 41 - 0.3 - 200 Internally Limited - 15 +10/-1 +10/-1 2000 -40 to 150 - 55 to 150 Unit V V mA A A mA mA V C C Table 5. Thermal Data Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Value 1.7 52 (1) Unit C/W C/W Note: 1. When mounted on a standard single-sided FR-4 board with 1 cm2 of Cu (at least 35m thick) connected to TAB. 3/13 VNQ5050K-E ELECTRICAL CHARACTERISTICS (8V Note: (**) Per each channel. Note: 2. PowerMOS leakage included. Table 7. Switching (VCC=13V) Symbol td(on) td(off) dVOUT/dt(on) dVOUT/dt(off) WON WOFF Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Turn-off Voltage Slope Switching energy losses at turn-on Switching energy losses at turn-off Test Conditions RL=6.5 RL=6.5 RL=6.5 RL=6.5 RL=6.5 RL=6.5 Min. Typ. 15 40 0.3 0.35 TBD TBD Max. Unit s s V/s V/s mJ mJ 4/13 VNQ5050K-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin (VSD=0) Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT= 1.6 mA, VSD=0V Normal Operation or VSD=5V, Status Leakage Current VSTAT= 5V Status Pin Input Normal Operation or VSD=5V, Capacitance VSTAT= 5V ISTAT= 1mA Status Clamp Voltage ISTAT= - 1mA Min Typ Max 0.5 10 100 5.5 -0.7 TBD Unit V A pF V V Table 9. Protections (see note 3) Symbol IlimH IlimL TTSD TR TRS THYST tSDL VDEMAG VON Parameter DC Short circuit current Short circuit current ing thermal cycling durVCC=13V 5V TRS + 1 TRS + 5 135 Tj>TTSD IOUT=2A; VIN=0; L=6mH IOUT=0.1A (see fig. 6) Tj= -40C...+150C Note: 3. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles Table 10. Openload Detection Symbol IOL tDOL(on) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Delay between INPUT falling edge and STATUS rising edge in Openload condition Openload OFF State Voltage Detection Threshold Output Short Circuit to Vcc Detection Delay at Turn Off Test Conditions VIN = 5V , 8V IOUT = 0A 200 500 1000 VOL tDSTKON VIN = 0V, 8V 3 4 tPOL V s 5/13 VNQ5050K-E Figure 5. OPEN LOAD STATUS TIMING (without external pull-up) VIN IOUT < IOL VOUT < VOL OPEN LOAD STATUS TIMING (with external pull-up) VIN IOUT < IOL VOUT > VOL VSTAT tDOL(on) tPOL VSTAT tDOL(on) OUTPUT STUCK TO Vcc VIN IOUT > IOL VOUT > VOL VIN OVER TEMP STATUS TIMING Tj > TTSD VSTAT VSTAT tDOL(on) tDSTKON tSDL tSDL Figure 6. Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) 6/13 VNQ5050K-E ELECTRICAL CHARACTERISTICS (continued) Table 11. Logic Input Symbol VIL IIL VIH IIH VI(hyst) VICL VSDL ISDL VSDH ISDH VSD(hyst) VSDCL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage STAT_DIS low level voltage Low level STAT_DIS current STAT_DIS high level voltage High level STAT_DIS current STAT_DIS hysteresis voltage STAT_DIS clamp voltage ISD=1mA ISD=-1mA VSD=2.1V 0.25 5.5 -0.7 TBD VSD=0.9V 1 2.1 10 IIN = 1mA IIN = -1mA VIN = 2.1V 0.25 5.5 -0.7 0.9 TBD VIN = 0.9V 1 2.1 10 Test Conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V Table 12. Truth Table CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Output Voltage > VOL Output Current < IOL INPUTn L H L H L H L H L H L H OUTPUTn L H L X L L L L H H L H STATUSn (VSD=0V) (1) H H H H H L X X L(2) H H(3) L Note: 1. If the VSD is high, the STATUS pin is in a high impedance. 2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. 3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge. 7/13 VNQ5050K-E Figure 7. Switching Characteristics VOUT 80% dVOUT/dt(on) tr 10% 90% dVOUT/dt(off) tf t INPUT td(on) td(off) t Table 13. Electrical Transient Requirements ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 I C C C C C C IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 8/13 VNQ5050K-E Figure 8. Application Schematic +5V +5V VCC Rprot STAT_DIS Dld Rprot C OUTPUTn Rprot STATUSn GND INPUTn RGND VGND DGND Note: Channels 2, 3 and 4 have the same internal circuit as channel 1. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 9/13 VNQ5050K-E Figure 9. Waveforms NORMAL OPERATION INPUT STAT_DIS LOAD CURRENT STATUS UNDERVOLTAGE VUSDhyst VCC INPUT STAT_DIS LOAD CURRENT STATUS VUSD undefined OPEN LOAD with external pull-up INPUT STAT_DIS LOAD VOLTAGE STATUS OPEN LOAD without external pull-up INPUT STAT_DIS LOAD VOLTAGE LOAD CURRENT STATUS IOUT VOUT >VOL VOL RESISTIVE SHORT TO Vcc, NORMAL LOAD INPUT STAT_DIS LOAD VOLTAGE STATUS tDSTKON IOUT>IOL VOUT >VOL VOL OVERLOAD OPERATION Tj INPUT STAT_DIS LOAD CURRENT STATUS ILIMH ILIML TR TTSD TRS current power limitation limitation thermal cycling SHORTED LOAD NORMAL LOAD 10/13 VNQ5050K-E PACKAGE MECHANICAL Table 14. PowerSSO-24TM Mechanical Data Symbol A A2 a1 b c D E e e3 G G1 H h L N X Y 3.9 6.1 0.55 10.1 millimeters Min 1.9 1.9 0 0.34 0.23 10.2 7.4 0.8 8.8 0.1 0.06 10.5 0.4 0.85 10 4.3 6.5 0.4 Typ Max 2.22 2.15 0.07 0.46 0.32 10.4 7.6 Figure 10. PowerSSO-24TM Package Dimensions 11/13 VNQ5050K-E REVISION HISTORY Table 1. Revision History Date Sep. 2004 Revision 1 - First issue. Description of Changes 12/13 VNQ5050K-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com (c) 13/13 |
Price & Availability of VNQ5050K-E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |